SV51006
2014.01.10
Single-ended I/O Termination
5-37
Figure 5-15: SSTL I/O Standard Termination
This figure shows the details of SSTL I/O termination on Stratix V devices. This is not applicable for SSTL-12,
SSTL-15, SSTL-125, and SSTL-135 I/O standards.
Termination
SSTL Class I
SSTL Class II
V TT
V TT
V TT
25 Ω
50 Ω
50 Ω 50 Ω
External
On-Board
Termination
Transmitter
Series OCT 50 Ω
50 Ω
VREF
50 Ω
V TT
Receiver
Transmitter
Series OCT 25 Ω
25 Ω
V TT
50 Ω
50 Ω
VREF
V TT
50 Ω
Receiver
OCT Transmit
50 Ω
VREF
50 Ω
VREF
Transmitter
Receiver
Transmitter
Receiver
V CCIO
FPGA
Parallel OCT
V TT
50 Ω
V CCIO
FPGA
Parallel OCT
OCT Receive
25 Ω
50 Ω
100 Ω
50 Ω
100 Ω
VREF
100 Ω
25 Ω
VREF
100 Ω
Transmitter
V CCIO
GND
V CCIO
Receiver
Transmitter
V CCIO
GND
V CCIO
Receiver
Series
OCT 50 Ω
100 Ω
VREF
100 Ω
Series
OCT 25 Ω
100 Ω
VREF
100 Ω
OCT in
50 Ω
50 Ω
Bidirectional
100 Ω
100 Ω
100 Ω
100 Ω
Pins
GND
VREF
GND
Series
OCT 50 Ω
GND
VREF
GND
Series
OCT 25 Ω
I/O Features in Stratix V Devices
FPGA
FPGA
FPGA
FPGA
Altera Corporation
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